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1
PRELIMINARY
CY7C09569V CY7C09579V
3.3V 16K/32K x 36 FLEx36TM Synchronous Dual-Port Static RAM
Features
* True dual-ported memory cells which allow simultaneous access of the same memory location * Two Flow-Through/Pipelined devices -- 16K x 36 organization (CY7C09569V) -- 32K x 36 organization (CY7C09579V) * 0.25-micron CMOS for optimum speed/power * Three modes -- Flow-Through -- Pipelined * * * * -- Burst Bus-Matching Capabilities on Right Port (x36 to x18 or x9) Byte-Select Capabilities on Left Port 100-MHz Pipelined Operation High-speed clock to data access 5/6/8 ns * 3.3V Low operating power -- Active = 250 mA (typical) -- Standby = 10 A (typical) * Fully synchronous interface for ease of use * Burst counters increment addresses internally -- Shorten cycle times -- Minimize bus noise * * * * * -- Supported in Flow-Through and Pipelined modes Counter Address Read Back via I/O lines Single Chip Enable Automatic power-down Commercial and Industrial Temperature Ranges Compact package -- 144-Pin TQFP (20 x 20 x 1.4 mm) -- 172-Ball BGA (1.0 mm pitch) (15 x 15 x .51 mm)
Logic Block Diagram
R/WL OEL B0-B3 CEL FT/PipeL Left Port Control Logic Right Port Control Logic
R/WR OER CER FT/PipeR BE
9 9 9
I/O0L-I/O 8L
9
I/O9L-I/O 17L
9
I/O Control
I/O Control
9 9
Bus Match
9/18/36
I/OR
I/O18L-I/O26L
9
I/O27L-I/O35L A0-A13/14L CLKL ADSL CNTENL CNTRSTL
[1]
BM SIZE
14/15
14/15
Counter/ Address Register Decode
True Dual-Ported RAM Array
Counter/ Address Register Decode
A0-A13/14R CLKR ADSR CNTENR CNTRSTR
[1]
Note: 1. A0-A13 for 16K; A0-A14 for 32K devices.
For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 November 1, 1999
PRELIMINARY
Functional Description
The CY7C09569V and CY7C09579V are high-speed 3.3V synchronous CMOS 16K and 32K x 36 dual-port static RAMs. Two ports are provided permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines allow for minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 5 ns (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flowthrough mode data will be available tCD1 = 15 ns after the address is clocked into the device. Pipelined output or flowthrough mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the external R/W LOW duration. The internal write pulse is self-timed to allow the shortest possible cycle times.
CY7C09569V CY7C09579V
A HIGH on CE for one clock cycle will power down the internal circuitry to reduce the static power consumption. In the pipelined mode, one cycle is required with CE LOW to reactivate the outputs. Counter Enable Inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's Address Strobe (ADS). When the port's Count Enable (CNTEN) is asserted, the address counter will increment on each LOW-to-HIGH transition of that port's clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter. All parts are available in 144-Pin Thin Quad Plastic Flatpack (TQFP) and 172-Ball Ball Grid Array (BGA) packages.
2
PRELIMINARY
Pin Configurations
144-Pin Thin Quad Flatpack (TQFP) Top View
I/O32L I/O31L VSS I/O30L I/O29L I/O28L I/O27L VDD I/O17L I/O16L I/O15L I/O14L VSS I/O13L I/O12L I/O11L I/O10L I/O9L I/O9R I/O10R I/O11R I/O12R I/O13R VSS I/O14R I/O15R I/O16R I/O17R VDD I/O27R I/O28R I/O29R I/O30R VSS I/O31R I/O32R
CY7C09569V CY7C09579V
I/O33L I/O34L I/O35L A0L A1L A2L A3L A4L A5L A6L A7L B0 B1 B2 B3 OEL R/WL VDD VSS VSS CEL CLKL ADSL CNTRSTL CNTENL FT/PIPEL A8L A9L A10L A11L A12L A13L [2] NC I/O26L I/O25L I/O24L
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
CY7C09569V (16K x 36) CY7C09579V (32K x 36)
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
I/O33R I/O34R I/O35R A0R A1R A2R A3R A4R A5R A6R A7R BM SIZE BE
vss
OER R/WR VDD VSS VSS CER CLKR ADSR CNTRSTR CNTENR FT/PIPER A8R A9R A10R A11R A12R A13R [3] NC I/O26R I/O25R I/O24R
Notes: 2. This pin is A14L for CY7C09579V. 3. This pin is A14R for CY7C09579V.
I/O23L I/O22L VSS
3
I/O5R I/O6R I/O7R I/O8R VDD I/O18R I/O19R I/O20R I/O21R VSS I/O22R I/O23R
I/O19L I/O18L VDD I/O8L I/O7L I/O6L
I/O21L I/O20L
I/O0L I/O0R I/O1R I/O2R I/O3R I/O4R VSS
I/O5L VSS I/O4L I/O3L I/O2L I/O1L
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PRELIMINARY
Pin Configurations (continued)
172-Ball Ball Grid Array (BGA) Top View 1 A B C D E F G H J K L M N P
I/O32L
CY7C09569V CY7C09579V
2
I/O30L
3
NC
4
VSS
5
I/O13L
6
VDD
7
I/O11L
8
I/O11R
9
VDD
10
I/O13R
11
VSS
12
NC
13
I/O30R
14
I/O32R
A0L
I/O33L
I/O29
I/O17L
I/O14L
I/O12L
I/O9L
I/O9R
I/O12R
I/O14R
I/O17R
I/O29R
I/O33R
A0R
NC
A1L
I/O31L
I/O27L
NC
I/O15L
I/O10L
I/O10R
I/O15R
NC
I/O27R
I/O31R
A1R
NC
A2L
A3L
I/O35L
I/O34L
I/O28L
I/O16L
VSS
VSS
I/O16R
I/O28R
I/O34R
I/O35R
A3R
A2R
A4L
A5L
NC
B0L
NC
NC
NC
NC
BM
NC
A5R
A4R
VDD
A6L
A7L
B1L
NC
NC
SIZE
A7R
A6R
VDD
OEL
B2L
B3L
CEL
CER
VSS
BE
OER
VSS
R/WL
A8L
CLKL
CLKR
A8R
R/WR
VSS
A9L
A10L
VSS
ADSL
NC
NC
ADSR
VSS
A10R
A9R
A11L
A12L
NC
CNTRSTL
NC
NC
NC
NC
CNTRSTR
NC
A12R
A11R
[2]
FT/PIPEL A13L CNTENL I/O26L I/O25L I/O19L VSS VSS I/O19R I/O25R I/O26R CNTENR
[3]
A13R FT/PIPER
NC
NC
I/O22L
I/O18L
NC
I/O7L
I/O2L
I/O2R
I/O7R
NC
I/O18R
I/O22R
NC
NC
I/O24L
I/O20L
I/O8L
I/O6L
I/O5L
I/O3L
I/O0L
I/O0R
I/3R
I/O5R
I/O6R
I/O8R
I/O20R
I/O24R
I/O23L
I/O21L
NC
VSS
I/O4L
VDD
I/O1L
I/O1R
VDD
I/O4R
VSS
NC
I/O21R
I/O23R
4
PRELIMINARY
Selection Guide
CY7C09569V CY7C09579V -100 fMAX2 (MHz) (Pipelined) Max. Access Time (ns) (Clock to Data, Pipelined) Typical Operating Current ICC (mA) Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) Typical Standby Current for ISB3 (A) (Both Ports CMOS Level) 100 5 250 30 10 A CY7C09569V CY7C09579V -83 83 6 240 25 10 A
CY7C09569V CY7C09579V
CY7C09569V CY7C09579V -67 67 8 230 25 10 A
Pin Definitions
Left Port A0L-A13/14L ADSL Right Port A0R-A13/14R ADSR Description Address Inputs (A0-A13 for 16K, A0-A14 for 32K devices). Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to assert the part using the externally supplied address on Address Pins. To load this address into the Burst Address Counter both ADS and CNTEN have to be LOW. ADS is disabled if CNTRST is asserted LOW Chip Enable Input. Clock Signal. This input can be free-running or strobed. Maximum clock input rate is fMAX. Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if CNTRST is asserted LOW. Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. Data Bus Input/Output. Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. Byte Select Inputs. Asserting these signals enable read and write operations to the corresponding bytes of the memory array. BM, SIZE BE VSS VDD Select Pins for Bus Matching. See Bus Matching for details. Big Endian Pin. See Bus Matching for details. Ground Input. Power Input.
CEL CLKL CNTENL CNTRSTL I/O0L-I/O 35L OEL R/WL FT/PIPEL B0-B3
CER CLKR CNTENR CNTRSTR I/O0R-I/O35R OER R/WR FT/PIPE R
5
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied .............................................-55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State ...........................-0.5V to VDD+0.5V DC Input Voltage...................................-0.5V to VDD+0.5V[4]
CY7C09569V CY7C09579V
Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 3.3V 165 mV 3.3V 165 mV
Shaded areas contain advance information.
Electrical Characteristics Over the Operating Range
CY7C09569V CY7C09579V -100 Parameter VOH VOL VIH VIL IOZ ICC ISB1 ISB2 ISB3 ISB4 Description Output HIGH Voltage (VDD = Min., IOH = -4.0 mA) Output LOW Voltage (VDD = Min., IOL= +4.0 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current Operating Current (VDD = Max., IOUT = 0 mA) Outputs Disabled Standby Current (Both Ports TTL Level) CEL & CER VIH, f = fMAX Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Standby Current (Both Ports CMOS Level) CEL & CER VDD-0.2V, f = 0 Standby Current (One Port CMOS Level) CEL | CER VIH, f = fMAX Com'l. Indust. Com'l. Indust. Com'l. Indust. Com'l. Indust. Com'l. Indust. 150 200 0.01 1 170 220 30 75 -10 250 2.0 0.8 10 385 -10 240 270 25 35 160 170 0.01 0.01 140 150 2.4 0.4 2.0 0.8 10 360 385 70 85 210 235 1 1 190 200 130 180 0.01 1 150 200 25 65 -10 230 2.4 0.4 2.0 0.8 10 340 -83 2.4 0.4 -67 V V V V A mA mA mA mA mA mA mA mA mA mA Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Shaded areas contain advance information.
Capacitance
Parameter CIN COUT
Note: 4. Pulse width < 20 ns.
Description Input Capacitance Output Capacitance
Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V
Max. 10 10
Unit pF pF
6
PRELIMINARY
CY7C09569V CY7C09579V
AC Test Load and Waveforms
3.3V OUTPUT Z0 = 50 C
[5]
R = 50 R1 = 590 OUTPUT VTH = 1.5V C = 5 pF R2 = 435
(a) Normal Load (Load 1)
(b) Three-State Delay (Load 2)
3.0V
ALL INPUT PULSES
VSS
10% 3 ns
90%
90% 10% 3 ns
7 tcd2 for 100 MHz (ns) 6 5 4 3 2 1 20 [6] 30
60
80 100
200
Capacitance (pF) (b) Load Derating Curve
Notes: 5. External AC Test Load Capacitance = 10 pF 6. (Internal I/O pad Capacitance = 10 pF) + AC Test Load
7
PRELIMINARY
Switching Characteristics Over the Operating Range
CY7C09569V CY7C09579V -100 Parameter fMAX1 fMAX2 tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSB tHB tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ[7, 8] tOHZ[7, 8] tCD1 tCD2 tCA1 tCA2 tDC tCKHZ tCKLZ
[7, 8] [7, 8]
CY7C09569V CY7C09579V
-83 Min. Max. 45 83 22 12 7.5 7.5 5 5 3 3 3 3 4 0.5 4 0.5 4 0.5 4 0.5 4 0.5 4 0.5 4 0.5 4 0.5 8 9 2 7 15 5 15 9 1 7 18 6 18 10 2 6 2 2 7 2 2 2 2 1 4 0.5 4 0.5 4 0.5 4 0.5 4 0.5 4 0.5 4 0.5 4 0.5 25 15 8.5 8.5 6.5 6.5 67
-67 Min. Max. 40 67 Unit MHz MHz ns ns ns ns ns ns 3 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 7 20 8 20 11 8 ns ns ns ns ns ns ns ns ns ns
Description fMax Flow-Through fMax Pipelined Clock Cycle Time - Flow-Through Clock Cycle Time - Pipelined Clock HIGH Time - Flow-Through Clock LOW Time - Flow-Through Clock HIGH Time - Pipelined Clock LOW Time - Pipelined Clock Rise Time Clock Fall Time Address Set-Up Time Address Hold Time Byte Select Set-Up Time Byte Select Hold Time Chip Enable Set-Up Time Chip Enable Hold Time R/W Set-Up Time R/W Hold Time Input Data Set-Up Time Input Data Hold Time ADS Set-Up Time ADS Hold Time CNTEN Set-Up Time CNTEN Hold Time CNTRST Set-Up Time CNTRST Hold Time Output Enable to Data Valid OE to Low Z OE to High Z Clock to Data Valid - Flow-Through Clock to Data Valid - Pipelined Clock to Counter Address Valid - Flow-Through Clock to Counter Address Valid - Pipelined Data Output Hold After Clock HIGH Clock HIGH to Output High Z Clock HIGH to Output Low Z
Min.
Max. 100
15 10 6.5 6.5 4 4
3.5 0.5 3.5 0.5 3.5 0.5 3.5 0.5 3.5 0.5 3.5 0.5 3.5 0.5 3.5 0.5 2 1
2 2 2
Notes: 7. This parameter is guaranteed by design, but it is not production tested. 8. Test conditions used are Load 2.
8
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)
CY7C09569V CY7C09579V -100 Parameter Port to Port Delays tCWDD tCCS Write Port Clock HIGH to Read Data Delay Clock to Clock Set-Up Time 30 9 35 10 Description Min. Max. -83 Min. Max.
CY7C09569V CY7C09579V
-67 Min. Max. 35 12 Unit ns ns
9
PRELIMINARY
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = V IL)[9, 10, 11, 12]
tCH1 CLK tCYC1 tCL1
CY7C09569V CY7C09579V
CE tSC B0-3 tHC tSB tHB tSC tHC
R/W tSW tSA ADDRESS DATAOUT tCKLZ tOHZ OE tOE tOLZ An tCD1 tHW tHA An+1 tDC Qn Qn+1 An+2 An+3 tCKHZ Qn+2 tDC
Read Cycle for Pipelined Operation (FT/PIPE = VIH)[9, 10, 11, 12]
tCH2 CLK tCYC2 tCL2
CE tSC B0-3 tHC tSC tSB tHB tHC
R/W tSW tSA ADDRESS DATAOUT An 1 Latency tHW tHA An+1 tCD2 Qn tCKLZ OE
tOE Notes: 9. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 10. ADS = VIL, CNTEN = VIL and CNTRST = VIH. 11. The output is disabled (high-impedance state) by CE=VIH following the next rising edge of the clock. 12. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
An+2 tDC Qn+1 tOHZ
An+3
Qn+2 tOLZ
10
PRELIMINARY
Switching Waveforms (continued)
Bus Match Read Cycle for Flow-Through Output (FT/PIPE = VIL)[9, 10, 11, 12, 13, 14]
tCH1 CLK tCYC1 tCL1
CY7C09569V CY7C09579V
CE tSC tHC
R/W tSW tSA ADDRESS DATAOUT tCKLZ OE LOW An tCD1 tHW tHA An tDC Qn 1st Cycle Qn 2nd Cycle Qn+1 1st Cycle tDC Qn+1 2nd Cycle An+1 An+1
Bus Match Read Cycle for Pipelined Operation (FT/PIPE = VIH)[9, 10, 11, 12, 13, 14]
tCYC2 tCH2 CLK tCL2
CE tSC R/W tSW tHW ADDRESS An tSA tHA tCLKZ DATAOUT 1 Latency OE LOW Qn tDC 1st Cycle Qn tDC 2nd Cycle Qn+1 tDC 1st Cycle An tCD2 An+1 tCD2 An+1 tCD2 tHC
Notes: 13. Timing shown is for x18 bus matching; x9 bus matching is similar with 4 cycles between address inputs. 14. See table "Right Port Operation " for data output on first and subsequent cycles.
11
PRELIMINARY
Switching Waveforms (continued)
Bank Select Pipelined Read[15, 16]
tCH2 CLKL tSA ADDRESS(B1) tSC CE(B1) tCD2 DATAOUT(B1) tSA ADDRESS(B2) A0 tHA A1 tSC CE(B2) tSC DATAOUT(B2) tCKLZ tHC tCD2 Q2 tCKHZ tSC Q0 tDC A2 tHC tHC tCD2 Q1 tDC A3 A4 tCKLZ tCKHZ tCD2 A0 tHC tHA A1 A2 A3 A4 tCYC2 tCL2
CY7C09569V CY7C09579V
A5
tCKHZ Q3
A5
tCD2 Q4 tCKLZ
Left Port Write to Flow-Through Right Port Read[16, 17, 18, 19, 20]
CLKL tSW R/WL tSA ADDRESSL tSD DATAINL CLKR R/WR ADDRESSR tSW tSA tHW tHA NO MATCH tCWDD DATAOUTR tDC VALID tDC tCD1 VALID VALID tCCS tCD1 MATCH tHD tHA NO MATCH tHW
MATCH
Notes: 15. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this data sheet. ADDRESS(B1) = ADDRESS(B2). 16. B0 = B1 = B2 = B3 = BM = SIZE = ADS = CNTEN = VIL, CNTRST = VIH. 17. The same waveforms apply for a right port write to flow-through left port read. 18. CE = B0 = B1 = B2 = B3 = ADS = CNTEN=VIL; CNTRST= VIH. 19. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to. 20. It t CCS maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid until tCCS + tCD1 (tCWDD does not apply in this case).
12
PRELIMINARY
Switching Waveforms (continued)
Pipelined Read-to-Write-to-Read (OE = VIL)[12, 21, 22, 23]
tCH2 CLK tCYC2 tCL2
CY7C09569V CY7C09579V
CE tSC tHC
tSW R/W tSW ADDRESS tSA DATAIN An tHA tCD2 Qn READ tHW An+1 An+2
tHW
An+2 tSD tHD
An+3
An+4
tCKHZ
Dn+2
tCKLZ
tCD2 Qn+3
DATAOUT
NO OPERATION
[11, 21, 22, 23]
WRITE
READ
Pipelined Read-to-Write-to-Read (OE Controlled)
tCH2 CLK tCYC2 tCL2
CE tSC tHC
tSW tHW R/W
tSW An
tHW An+1 tHA An+2 tSD tHD Dn+2 tCD2 Dn+3 tCKLZ Qn tOHZ tCD2 Qn+4 An+3 An+4 An+5
ADDRESS tSA DATAIN
DATAOUT
OE READ WRITE READ
Notes: 21. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. 22. CE = ADS = CNTEN = VIL; CNTRST = VIH. 23. During "No operation," data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
13
PRELIMINARY
Switching Waveforms (continued)
Bus Match Pipelined Read-to-Write-to-Read (OE = VIL)[11,13, 14, 21, 22, 23, 24]
tCYC2
CY7C09569V CY7C09579V
CLK tCH2 tCL2 CE tSC tHC
R/W tSW ADDRESS tSA DATAOUT tCD2 DATAIN tSD READ READ 1st Cycle READ 2nd Cycle No Operation An tHA 1st Word Qn tCD2 2nd Word Qn tCKHZ 1st Word Dn+2 tHD 2nd Word Dn+2 tCD2 tDC tCKLZ 1st Word Qn+3 2nd Word Qn+3 tHW An An+1 An+1 An+2 An+2 An+3 An+3 An+4 An+4
WRITE
1st Cycle
WRITE
2nd Cycle
READ
READ 1st Cycle
READ 2nd Cycle
Note: 24. BM, SIZE, and BE must be reconfigured 1 cycle before operation is guaranteed. BM, SIZE, and BE should remain static for any particular port configuration.
14
PRELIMINARY
Switching Waveforms (continued)
Flow-Through Read-to-Write-to-Read (OE = VIL)[10, 12, 13, 14, 22, 23]
tCH1 CLK tCYC1 tCL1
CY7C09569V CY7C09579V
CE
tSW R/W tSW ADDRESS tSA DATAIN tCD1 Qn tDC READ An tHA tCD1 Qn+1 tCKHZ NO OPERATION tHW An+1 An+2 tSD Dn+2 An+2
tHW
An+3 tHD tCD1
An+4
tCD1 Qn+3
DATAOUT
tCKLZ WRITE
tDC READ
Flow-Through Read-to-Write-to-Read (OE Controlled)[10, 12, 21, 22, 23]
tCH1 CLK tCYC1 tCL1
CE
tSW R/W tSW An ADDRESS tSA DATAIN tCD1 Qn tOHZ tHA tDC tSD Dn+2 tHW An+1 An+2
tHW
An+3 tHD Dn+3
An+4
An+5
tOE tCD1 Qn+4 tCKLZ tDC
tCD1
DATAOUT
OE READ WRITE READ
15
PRELIMINARY
Switching Waveforms (continued)
Bus Match Flow-Through Read-to-Write-to-Read (OE = VIL)[10, 11, 13, 14, 22, 23, 24]
tCYC1 tCH1 CLK tSC CE tSW tHW R/W tSA tHA tSW tHW tHC tCL1
CY7C09569V CY7C09579V
ADDRESS
An
An
An+1
An+1 tSD tHD
An+1
An+1
An+1
An+2
DATAIN tCD1
tCD1 tDC Qn 1st Word tCKHZ
Dn+1 1st Word
Dn+1 2nd Word tCD1 Qn+1 tCKLZ tDC READ 2nd Cycle tCD1 Qn+1
DATAOUT
Qn 2nd Word
READ 1st Cycle
READ 2nd Cycle
No Operation
WRITE 1st Cycle
WRITE 2nd Cycle
READ 1st Cycle
16
PRELIMINARY
Switching Waveforms (continued)
Pipelined Read with Address Counter Advance[25]
tCYC2 tCL2
CY7C09569V CY7C09579V
tCH2 CLK tSA ADDRESS tSAD ADS An
tHA
tHAD
tSAD CNTEN tSCN DATAOUT Qx-1 READ EXTERNAL ADDRESS tHCN Qx tDC READ WITH COUNTER tCD2 Qn tSCN Qn+1
tHAD
tHCN Qn+1 Qn+2
COUNTER HOLD
READ WITH COUNTER
Flow-Through Read with Address Counter Advance[25]
tCYC1 tCL1
tCH1 CLK tSA ADDRESS tSAD ADS An
tHA
tHAD tSAD tHAD
CNTEN tSCN tHCN tCD1 Qx tDC READ EXTERNAL ADDRESS Qn Qn+1 Qn+2 COUNTER HOLD READ WITH COUNTER tSCN tHCN
DATAOUT
Qn+2
Qn+3 READ WITH COUNTER
Note: 25. CE = OE = VIL ; R/W = CNTRST = VIH.
17
PRELIMINARY
Switching Waveforms (continued)
Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[26, 27]
tCH2 CLK tSA ADDRESS An tHA tCYC2 tCL2
CY7C09569V CY7C09579V
INTERNAL ADDRESS tSAD ADS tHAD
An
An+1
An+2
An+3
An+4
CNTEN tSCN DATAIN tSD Dn tHD WRITE EXTERNAL ADDRESS tHCN Dn+1 WRITE WITH COUNTER Dn+1 Dn+2 Dn+3 Dn+4
WRITE COUNTER HOLD
WRITE WITH COUNTER
Notes: 26. CE= B0 = B1 = B2 = B3 = R/W = VIL; CNTRST = VIH. 27. The "Internal Address" is equal to the "External Address" when ADS = CNTEN = VILand CNTRST=VIH.
18
PRELIMINARY
Switching Waveforms (continued)
Counter Reset (Pipelined Outputs)[11, 21, 28, 29, 30]
tCYC2 tCH2 tCL2 CLK tSA ADDRESS INTERNAL ADDRESS An tHA Am
CY7C09569V CY7C09579V
Ap
Ax tSW tHW
0
1
An
Am
Ap
R/W
ADS
CNTEN tSRST tHRST CNTRST tSD DATAIN
[30]
tHD
D0 tCD2
tCD2 Q0 Q1 Qn
DATAOUT tCKLZ COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1
READ ADDRESS An
READ ADDRESS Am
Notes: 28. CE = B0 = B1 = B2 = B3 = VIL . 29. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. 30. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATAOUT should be in the High-Impedance state during a valid WRITE cycle.
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PRELIMINARY
Switching Waveforms (continued)
Counter Reset (Flow-Through Outputs)[21, 23, 28, 29, 30]
tCH2 CLK tSA ADDRESS An tHA tCYC2 tCL2
CY7C09569V CY7C09579V
An+1
INTERNAL ADDRESS
AX tSW tHW
0
1
An
An+1
R/W
ADS
CNTEN tSRST tHRST CNTRST
tSD D0
tHD
DATAIN
tCD1 DATAOUT COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 Q0 READ ADDRESS 1 Q1 READ ADDRESS n Qn
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PRELIMINARY
Switching Waveforms (continued)
Pipelined Read of State of Address Counter [31, 32,33]
tCYC2 tCH2 tCL2 CLK tSA tHA ADDRESS INTERNAL ADDRESS tSAD tHAD ADS tSCN tHCN CNTEN tSCN tHCN DATAOUT Qx-2 LOAD EXTERNAL ADDRESS tCYC1 tCH1 tCL1 CLK tSA tHA ADDRESS INTERNAL ADDRESS tSAD tHAD ADS tSCN tHCN tSCN CNTEN tCA1 DATAOUT Qx Qn tDC LOAD EXTERNAL ADDRESS READ COUNTER ADDRESS An Qn+1 READ WITH COUNTER COUNTER HOLD Qn+2 tSCN tHCN tHCN tSAD tHAD An Qx-1 Qn tCA2 An READ WITH COUNTER tSCN tHCN tSAD tHAD An
CY7C09569V CY7C09579V
An
An+1
An+2
Qn+1
Qn+2
tDC READ COUNTER ADDRESS
[31, 32, 34]
COUNTER HOLD
READ WITH COUNTER
Flow-Through Read of State of Address Counter
An
An+1
An+2
An+3
Qn+3
READ WITH COUNTER
Notes: 31. CE = OE = VIL ; R/W = CNTRST = VIH. 32. When reading ADDRESSOUT in x9 Bus Match mode, readout of AN is extended by 1 cycle. 33. For Pipelined address counter read, signals from address counter operation table from must be valid for 2 consecutive cycles for x36 and x18 mode and for 3 consecutive cycles for x9 mode. 34. For flow-through address counter read, signals from address counter operation table must be valid for consecutive cycles for x36.
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PRELIMINARY
Read/Write and Enable Operation[35, 36, 37]
Inputs OE X X L H X CLK CE H L L L R/W X L H X Outputs I/O0-I/O35 High-Z DIN DOUT High-Z
CY7C09569V CY7C09579V
Operation Deselected[38] Write Read[38] Outputs Disabled
Address Counter Control Operation[35, 39]
Address X An An X X Previous Address X X An An An CLK OE X X L X X R/W X X H X X ADS X L L H H CNTEN X L H H L CNTRST L H H H H Mode Reset Load Hold + Read Hold Increment Operation Counter Reset Address Load into Counter External Address Blocked Counter Address Readout External Address Blocked Counter Disabled Counter Increment
Notes: 35. "X" = "don't care," "H" = VIH, "L" = VIL . 36. ADS, CNTEN, CNTRST = "don't care." 37. OE is an asynchronous input signal. 38. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle. 39. Counter operation is independent of CE.
22
PRELIMINARY
Right Port Configuration[24, 40]
BM 0 1 1 SIZE 0 0 1 Configuration x36 x18 x9
CY7C09569V CY7C09579V
I/O Pins used I/O0R-35R I/O0R-17R I/O0R-8R
Right Port Operation[41]
Configuration x18 x18 x9 x9 BE 0 1 0 1 Data on 1st Cycle DQ0R-17R DQ18R-35R DQ0R-8R DQ27R-35R Data on 2nd Cycle DQ18R-35R DQ 0R-17R DQ 9R-17R DQ18R-26R Data on 3rd Cycle DQ18R-26R DQ9R-17R Data on 4th Cycle DQ27R-35R DQ 0R-8R
Readout of Internal Address Counter[42]
Configuration Left Port x36 Right Port x36 Right Port x18 Right Port x9 Address on 1st Cycle A0L-14L A0R-14R WA, A0R-14R A6R-14R I/O Pins used on 1st Cycle I/O3L-17L I/O3R-17R I/O2R-17R I/O0R-8R Address on 2nd Cycle BA, WA, A0R-5R I/O Pins used on 2nd Cycle I/O 1R-8R
Left Port Operation
Control Pin B0 B1 B2 B3
Notes: 40. In x36 mode, BE input is a "don't care". 41. DQ represents data output of the chip. 42. x18 and x9 configuration apply to right port only.
Effect I/O0-8 Byte Control I/O9-17 Byte Control I/O18-26 Byte Control I/O27-35 Byte Control
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PRELIMINARY
Counter Operation
CY7C09569V CY7C09579V
BE
The CY7C09569V/09579V Dual-Port RAM (DPRAM) contains on-chip address counters (one for each port) for the synchronous members of the product family. Besides the main x36 format, the right port allows bus matching (x18 or x9, userselectable). An internal sub-counter provides the extra addresses required to sequence out the 36-bit word in 18-bit or 9-bit increments. The sub-counter counts up in the "Little Endian" mode, and counts down if the user has chosen the "Big Endian" mode. For a x36 format (the only active format on the left port), each address counter in the CY7C09579V uses addresses (A0-14). For the right port (allowing for the bus-matching feature), a maximum of two address bits (out of a 2-bit sub-counter) are added. 1. ADSL/R (pin #23/86) is a port's address strobe, allowing the loading of that port's burst counters if the corresponding CNTENL/R pin is active as well. 2. CNTENL/R (pin #25/84) is a port's count enable, provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications; when asserted, the address counter will increment on each positive transition of that port's clock signal. 3. CNTRSTL/R (pin #24/85) is a port's burst counter reset. A new read-back (Hold+Read Mode) feature has been added, which is different between the left and right port due to the bus matching feature provided only for the right port. In read-back mode the internal address of the counter will be read from the data I/Os as shown in Figure 1.
x36 /
BUS MODE
CY7C09569V CY7C09579V 16K/32Kx36 Dual Port
9 / 9 / 9 / 9 /
x9, x18, x36 /
BM SIZE
Figure 2. Bus Match Operation Diagram The Bus Match Select (BM) pin works with Bus Size Select (SIZE) and Big Endian Select (BE) to select the bus width (long-word, word, or byte) and data sequencing arrangement for the right port of the dual-port device. A logic "0" applied to both the Bus Match Select (BM) pin and to the Bus Size Select (SIZE) pin will select long-word (36-bit) operation. A logic "1" level applied to the Bus Match Select (BM) pin will enable whether byte or word bus width operation on the right port I/Os depending on the logic level applied to the SIZE pin. The level of Bus Match Select (BM) must be static throughout normal device operation. The Bus Size Select (SIZE) pin selects either a byte or word data arrangement on the right port when the Bus Match Select (BM) pin is HIGH. A logic "1" on the SIZE pin when the BM pin is HIGH selects a byte bus (9-bit) data arrangement). A logic "0" on the SIZE pin when the BM pin is HIGH selects a word bus (18-bit) data arrangement. The level of the Bus Size Select (SIZE) must also be static throughout normal device operation. The Big Endian Select (BE) pin is a multiple-function pin during word or byte bus selection (BM = 1). BE is used in Big Endian Select mode to determine the order by which bytes (or words) of data are transferred through the right data port. A logic "0" on the BE pin will select Little Endian data sequencing arrangement and a logic "1" on the BE pin will select a Big Endian data sequencing arrangement. Under these circumstances, the level on the BE pin should be static throughout dualport operation. Long-Word (36-bit) Operation Bus Match Select (BM) and Bus Size Select (SIZE) set to a logic "0" will enable standard cycle long-word (36-bit) operation. In this mode, the right port's I/O operates essentially in an identical fashion to the left port of the dual-port SRAM. However no Byte Select control is available. All 36 bits of the longword are shifted into and out of the right port's I/O buffer stages. All read and write timing parameters may be identical with respect to the two data ports. When the right port is configured for a long-word size, Big- Endian Select (BE) pin has no application and their inputs are "don't care"[43] for the external user. Word (18-bit) Operation Word (18-bit) bus sizing operation is enabled when Bus Match Select (BM) is set to a logic "1" and the Bus Size Select (SIZE) pin is set to a logic "0". In this mode, 18 bits of data are ported
Address Read-Back
CY7C09569V CY7C09579V RAM ARRAY
_______
______________
____________
Figure 1. Counter Operation Diagram
Bus Match Operation
The right port of the CY7C09569V/09579V 16K/32Kx36 dualport SRAM can be configured in a 36-bit long-word, 18-bit word, or 9-bit byte format for data I/O. The data lines are divided into four lanes, each consisting of 9 bits (byte-size data lines).
Note: 43. Even though a logic level applied to a "don't care" input will not change the logical operation of the dual-port, inputs that are temporarily a "don't care" (along with unused inputs) must not be allowed to float. They must be forced either HIGH or LOW.
24
PRELIMINARY
through I/O 0R-17R. The level applied to the Big Endian (BE) pin determines the right port data I/O sequencing order (Big Endian or Little Endian). During word (18-bit) bus size operation, a logic LOW applied to the BE pin will select Little Endian operation. In this case, the least significant data word is read from the right port first or written to the right port first. A logic "1" on the BE pin during word (18-bit) bus size operation will select Big Endian operation resulting in the most significant data word being transferred through the right port first. Internally, the data will be stored in the appropriate 36-bit LSB or MSB I/O memory location. Device operation requires a minimum of two clock cycles to read or write during word (18-bit) bus size operation. An internal sub-counter automatically increments the right port multiplexer control when Little or Big Endian operation is in effect. Byte (9-bit) Operation Byte (9-bit) bus sizing operation is enabled when Bus Match Select (BM) is set to a logic "1" and the Bus Size Select (SIZE)
CY7C09569V CY7C09579V
pin is set to a logic "1". In this mode, 9 bits of data are ported through I/O0R-8R. Big Endian and Little Endian data sequencing is available for dual-port operation. The level applied to the Big Endian pin (BE) under these circumstances will determine the right port data I/O sequencing order (Big or Little Endian). A logic LOW applied to the BE pin during byte (9-bit) bus size operation will select Little Endian operation. In this case, the least significant data byte is read from the right port first or written to the right port first. A logic "1" on the BE pin during byte (9-bit) bus size operation will select Big Endian operation resulting in the most significant data word to be transferred through the right port first. Internally, the data will be stored in the appropriate 36-bit LSB or MSB I/O memory location. Device operation requires a minimum of four clock cycles to read or write during byte (9bit) bus size operation. An internal sub-counter automatically increments the right port multiplexer control when Little or Big Endian operation is in effect. When transferring data in byte (9bit) bus match format, the unused I/O pins (I/O9RQ-35R) are three-stated.
25
PRELIMINARY
Ordering Information
16K x36 3.3V Synchronous Dual-Port SRAM Speed (ns) 100 83 Ordering Code CY7C09569V-100AC CY7C09569V-100BAC CY7C09569V-83AC CY7C09569V-83AI CY7C09569V-83BAC CY7C09569V-83BAI 67 CY7C09569V-67AC CY7C09569V-67BAC 32K x36 3.3V Synchronous Dual-Port SRAM Speed (ns) 100 83 Ordering Code CY7C09579V-100AC CY7C09579V-100BAC CY7C09579V-83AC CY7C09579V-83AI CY7C09579V-83BAC CY7C09579V-83BAI 67 CY7C09579V-67AC CY7C09579V-67BAC
Shaded areas contain advance information.
CY7C09569V CY7C09579V
Package Name A144 BA172 A144 A144 BA172 BA172 A144 BA172
Package Type 144-Pin Thin Quad Flat Pack 172-Ball Ball Grid Array (BGA) 144-Pin Thin Quad Flat Pack 144-Pin Thin Quad Flat Pack 172-Ball Ball Grid Array (BGA) 172-Ball Ball Grid Array (BGA) 144-Pin Thin Quad Flat Pack 172-Ball Ball Grid Array (BGA)
Operating Range Commercial Commercial Commercial Industrial Commercial Industrial Commercial Commercial
Package Name A144 BA172 A144 A144 BA172 BA172 A144 BA172
Package Type 144-Pin Thin Quad Flat Pack 172-Ball Ball Grid Array (BGA) 144-Pin Thin Quad Flat Pack 144-Pin Thin Quad Flat Pack 172-Ball Ball Grid Array (BGA) 172-Ball Ball Grid Array (BGA) 144-Pin Thin Quad Flat Pack 172-Ball Ball Grid Array (BGA)
Operating Range Commercial Commercial Commercial Industrial Commercial Industrial Commercial Commercial
Document #: 38-00743-A
26
PRELIMINARY
CY7C09569V CY7C09579V
Package Diagrams
144-Pin Plastic Thin Quad Flat Pack (TQFP) A144
51-85047-A
27
PRELIMINARY
Package Diagrams (continued)
172-Ball BGA BB172
CY7C09569V CY7C09579V
51-85114
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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